Abhishek Kumar Jain


Email: jain7@llnl.gov
Phone: +19254224809


Abhishek is a Postdoctoral Research Staff Member at the Center for Applied Scientific Computing at Lawrence Livermore National Laboratory (LLNL). His research interests include reconfigurable computing, throughput-oriented coarse-grained FPGA overlays, multiprocessor system-on-chip, high level synthesis, electronic design automation, near-memory processing, high performance accelerators and data-intensive computing architectures. He recently completed his Doctorate at Nanyang Technological University, Singapore where he developed techniques for virtualizing FPGA fabrics and for reducing the area and performance overheads in coarse-grained FPGA overlays.

Abhishek joined LLNL in April of 2017 after earning his Ph.D. in Computer Engineering from Nanyang Technological University, Singapore. Prior to his Ph.D., he completed Bachelors of Technology with Honors in Electronics and Communication Engineering from Indian Institute of Information Technology, Allahabad in 2012. For his dissertation work, he worked as an intern at STMicroelectronics, India. Prior to that he was awarded MITACS Globalink Scholarship to pursue research work at Electrical and Computer Engineering Department, University of Alberta, Canada in May, 2011.

Publications

A. K. Jain, D. L. Maskell, and S. A. Fahmy, “Resource-Aware Just-in-Time OpenCL Compiler for Coarse-Grained FPGA Overlays”, in Proceedings of the Third International Workshop on Overlay Architectures for FPGAs (OLAF), Held in conjunction with FPGA 2017, Monterey, CA, USA, Feb 2017.

A. K. Jain, D. L. Maskell, and S. A. Fahmy, “Are Coarse-Grained Overlays Ready for General Purpose Application Acceleration on FPGAs?”, in Proceedings of the IEEE International Conference on Pervasive Intelligence and Computing, Auckland, New Zealand, August 2016.

X. Li, A. K. Jain, D. L. Maskell, and S. A. Fahmy, “An Area-Efficient FPGA Overlay using DSP Block based Time-multiplexed Functional Units”, in Proceedings of the Second International Workshop on Overlay Architectures for FPGAs (OLAF), Held in conjunction with FPGA 2016, Monterey, CA, USA, Feb 2016. 

A. K. Jain, X. Li, P. Singhai, D. L. Maskell, and S. A. Fahmy, “DeCO: A DSP Block Based FPGA Accelerator Overlay With Low Overhead Interconnect”, in Proceedings of the IEEE International Symposium on Field Programmable Custom Computing Machines (FCCM), Washington, DC, May 2016.

A. K. Jain, D. L. Maskell, and S. A. Fahmy, “Throughput Oriented FPGA Overlays Using DSP Blocks”, in Proceedings of the Design, Automation and Test in Europe Conference (DATE), Dresden, Germany, March 2016, pp. 1628–1633.

A. K. Jain, X. Li, S. A. Fahmy, and D. L. Maskell, “Adapting the DySER Architecture with DSP Blocks as an Overlay for the Xilinx Zynq”, in Proceedings of the International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART), Boston, MA, June 2015.

A. K. Jain, S. A. Fahmy, and D. L. Maskell, “Efficient Overlay Architecture Based on DSP Blocks”, in Proceedings of the IEEE International Symposium on Field Programmable Custom Computing Machines (FCCM), Vancouver, Canada, May 2015, pp. 25–28.

A. K. Jain, K. D. Pham, J. Cui, S. A. Fahmy, and D. L. Maskell, "Virtualized Execution and Management of Hardware Tasks on a Hybrid ARM-FPGA Platform", in Journal of Signal Processing Systems, vol. 77, no. 1-2, pp. 61–76, October 2014, Springer. 

K. D. Pham, A. K. Jain, J. Cui, S. A. Fahmy, and D. L. Maskell, "Microkernel Hypervisor for a Hybrid ARM-FPGA Platform" in Proceedings of the IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), Washington, DC, June 2013, pp. 219-226.